Ball grid array (BGA) packaging technology is an advanced semiconductor packaging technology, which is characterized in that a semiconductor chip is mounted on a front surface of a substrate, and a plurality of conductive elements such as solder balls are arranged in a matrix array, customarily referred to as ball grid array, on a back surface of the substrate. The ball grid array allows the semiconductor package to be bonded and electrically connected to an external printed circuit board (PCB) or other electronic devices.
A typical plastic ball grid array (PBGA) semiconductor package, as disclosed in U.S. Pat. Nos. 5,640,048, 5,650,660, 5,739,588 and 5,801,440, is shown with its cross-sectional view in FIG. 1. This PBGA package comprises (a) a substrate 100, (b) a semiconductor chip 120, (c) a plurality of bonding wires 130, (d) an encapsulation body 140, and (e) a ball grid array 150 comprising a plurality of array-arranged solder balls 15.
In the PBGA package, the substrate 100 comprises an insulating dielectric layer 110 such as a resin core. The dielectric layer 110 has a front surface 111 and a back surface 112, wherein the front surface 111 is formed with a chip mounting area 108 for accommodating the chip 120, and the chip mounting area 108 is made of a conductive material to serve as a ground paddle. A plurality of conductive traces 101 are formed on the front surface 111 and the back surface 112 of the dielectric layer 110, wherein the conductive traces 101 on the front surface 111 are located around the chip mounting area 108 and covered by an insulating solder mask layer 102. Terminals of the conductive trace 101 on the front surface 111 of the dielectric layer 110 are exposed from the solder mask layer 102 to form bonding fingers 103 where the bonding wires 130 are bonded. Terminals of the conductive trace 101 on the back surface 112 of the dielectric layer 110 form ball pads 104 where the solder balls 15 are implanted. With the bonding wires 130 bonded to the corresponding bonding fingers 103, electronic signals from the chip 120 can be transmitted through the bonding wires 130, the conductive traces 101 on the front surface 111 of the dielectric layer 110, and conductive vias 105 penetrating the dielectric layer 110, to the solder balls 15 on the back surface 112 of the dielectric layer 110 and finally to an external device (such as PCB) bonded to the solder balls 15, such that the chip 120 is electrically connected to the external device via the ball grid array 150 comprising the plurality of solder balls 15. Further, the chip 120, bonding wires 130, bonding fingers 103, and a part of the surface of the solder mask layer 102 are encapsulated and protected by the encapsulation body 140.
Furthermore, the chip 120 is adhered via a conductive adhesive 160 such as silver adhesive to the chip mounting area 108 serving as the ground paddle, such that the chip 120 is grounded to a ground plane (not shown) in the dielectric layer (resin core) 110 of the substrate 100 through the conductive adhesive 160 and the chip mounting area (ground paddle) 108.
To comply with the requirements such as high performance, portability, light-weight and size compactness for consumer electronic devices, a chip scale package (CSP) such as thin and fine-pitch ball grid array (TFBGA) package, having a smaller substrate and more I/O (input/output) terminals than the PBGA package, has been developed as disclosed in U.S. Pat. No. 5,592,025. This compact CSP with a high-density circuit layout is shown in FIGS. 2 and 3, whose structure is similar to that of the PBGA package shown in FIG. 1, except that in the CSP, the surface area of the substrate 200 is decreased, and the number of conductive traces 201 for inputting/outputting signals to/from the chip 220 and the number of bonding fingers 203 and ball pads 204 formed at the terminals of the conductive traces 201 are increased. Further, due to the reduced surface area of the substrate 200, a part of the conductive traces 201 in the CSP must be arranged in the chip mounting area 280 and underneath the chip 220, and these conductive traces 201 are extended to expose their terminals from the chip mounting area 280 to thus form the bonding finger 203 for bonding the bonding wires 230. As a result, unlike the PBGA package, the chip mounting area of the CSP cannot entirely serve as the ground paddle, making the limited surface area of the substrate 200 be in good use. Therefore, as shown in FIGS. 2 and 3, the ground paddle 208 is reduced to a size that would not interfere with the conductive traces 201 disposed in the chip mounting area 280. A plurality of ground traces 218 are extended from the ground paddle 208 to outside the chip mounting area 280, and exposed terminals of the ground traces 218 serve as ground pads 219 to allow the chip 220 to be grounded to the ground paddle 208 via bonding wires (not shown) bonded to the ground pads 219. Moreover, the chip 220 in CSP is mounted on the chip mounting area 280 via an insulating adhesive 260, instead of the conductive adhesive 160 used in the PBGA package, so as to prevent short circuit between the chip 220 and the ground paddle 208 or between the adjacent conductive traces 201.
Moreover, in order to avoid signal delays due to uneven lengths of the conductive traces, an attempt is made to prepare all the conductive traces having the same length, and to dispose elongated portions of the conductive traces in the chip mounting area, such that similarly to the above, the conductive traces with the elongated portions are arranged underneath the semiconductor chip and extended out of the chip mounting area.
However, when the semiconductor package having the conductive traces extended out of the chip mounting area, has completed the packaging process and is subject to a high temperature environment for example in a reliability test or a reflow-soldering process during solder ball implantation, due to mismatch in coefficient of thermal expansion (CTE) between the chip and the substrate, the substrate and the chip mounted on the chip mounting area of the substrate would respectively generate different degrees of thermal expansion, resulting in thermal stress between the substrate and the chip. In this case, the peripheral area of the chip, especially the positions located the most far away from the center of the chip, encounter the greatest thermal stress. As a result, the conductive traces on the peripheral area of the chip may be cracked or broken for example the cracked or broken portions 209 shown in FIGS. 2 and 3, which thereby degrades the reliability and yield of the semiconductor package.